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| STLC2411 BLUETOOTHTM BASEBAND PRELIMINARY DATA 1 FEATURES Pin to pin compatible with the previous version STLC2410B Ericsson Technology Licensing Baseband Core (EBC) BluetoothTM specification compliance: V1.1 and V1.2 Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection Oriented (logical transport) link Synchronous Connection Oriented (SCO) links: 2 simultaneous SCO channels Supports Pitch-Period Error Concealment (PPEC) - Improves speech quality in the vicinity of interference - Improves coexistence with WLAN - Works at receiver, no Bluetooth implication Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave Faster Connection: Interlaced scan for Page and Inquiry scan, first FHS without random backoff, RSSI used to limit range Extended SCO (eSCO) links Standard BlueRF bus interface QoS Flush Clock support - System clock input: any integer value from 12 ... 33 MHz - LPO clock input at 3.2 and 32 kHz or via the embedded 32 kHz crystal oscillator cell ARM7TDMI 32-bit CPU Memory organization - 64KByte on-chip RAM - 4KByte on-chip boot ROM - Programmable external memory interface (EMI) - Supports byte and half word access - Supports up to 3 external RAM banks (1 Mbyte/ bank) - Supports up to 2 Mbyte external flash memory Low power architecture with 2 different low power levels: - Sleep Mode - Deep Sleep Mode HW support for packet types - ACL: DM1, 3, 5 and DH1, 3, 5 - SCO: HV1, 3 and DV Figure 1. Package TFBGA132 (8x8x1.2mm) Table 1. Order Codes Part Number STLC2411 Package TFBGA132 Temp. Range -40 to +85 C - eSCO: EV3, 5 Communication interfaces - Synchronous Serial Interface, supporting up to 32 bit data and different industry standards - Two enhanced 16550 UARTs with 128 byte FIFO depth - 12Mbps USB interface - Fast master I2C bus interface - Multi slot PCM interface - 16 programmable GPIOs - 2 external interrupts and various interrupt possibilities through other interfaces Ciphering support for up to 128-bit key Efficient support for WLAN coexistence in collocated scenario Receiver Signal Strength Indication (RSSI) support for power-controlled links Separate control for external power amplifier (PA) for class1 power support. Software support - Low level (up to HCI) stack or embedded stack with profiles - Support of UART and USB HCI transport layers Compliant to automotive specification AEC-Q100 1.1 Applications Features Typical applications in which the STLC2411 can be used are: Portable computers, PDA Modems Handheld data transfer devices Cameras Computer peripherals Other type of devices that require the wireless communication provided by BluetoothTM Cable replacement June 2004 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. REV. 1 1/25 STLC2411 2 DESCRIPTION The STLC2411 offers a compact and complete solution for short-range wireless connectivity. It incorporates all the lower layer functions of the BluetoothTM protocol. The microcontroller allows the support of all data packets of BluetoothTM in addition to voice. The embedded controller can be used to run the BluetoothTM protocol and application layers if required. The software is located in an external memory accessed through the external memory interface. 3 QUICK REFERENCE DATA 3.1 Absolute Maximum Ratings Operation of the device beyond these conditions is not guaranteed. Sustained exposure to these limits will adversely affect device reliability. Table 2. Absolute Maximum Ratings Symbol VDD VDDIO VIN Tstg Tlead Supply voltage core Supply voltage I/O Input voltage on any digital pin Storage temperature Lead temperature < 10s VSS - 0.5 -65 Conditions Min VSS - 0.5 Max 2.5 4 VDDIO + 0.3 +150 +250 Unit V V V C C 3.2 Operating Ranges Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied. Table 3. Operating Ranges Symbol VDD VDDIO_RADIO VDDIO Tamb Conditions Supply voltage digital core and emi pads Supply voltage radio interface (Values are given for the STLC2150 BT radio.) Supply voltage digital IO Operating ambient temperature Min 1.55 2.7 1.65 -40 Typ 1.8 3.3 3.3 Max 1.95 3.6 3.6 +85 Unit V V V C 3.3 I/O specifications Depending on the interface, the I/O voltage is typical 1.8V (interface to the flash memory) or typical 3.3V (all the other interfaces). These I/Os comply with the EIA/JEDEC standard JESD8-B. 3.3.1 Specifications for 3.3V I/Os Table 4. LVTTL DC Input Specification (3V 2/25 STLC2411 Table 5. LVTTL DC Output Specification (3V High level output voltage Ioh =-X mA Note: X is the source/sink current under worst-case conditions according to the drive capability. (See table 8, pad information for value of X). 3.3.2 Specifications for 1.8V I/Os Table 6. DC Input Specification (1.55V Table 7. DC Output Specification (1.55V Note: X is the source/sink current under worst-case conditions according to the drive capability. (See table 8, pad information for value of X). 3.4 Current Consumption Table 8. Typical power consumption of the STLC2411 and External STM Flash (M28R400CB) using UART (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) (Indicative only) Core STLC2411 State Slave Standby (no low power mode) Standby (low power mode enabled) ACL connection (no transmission) ACL connection (data transmission) SCO connection (no codec connected) Inquiry and Page scan (low power mode enabled) Low Power mode (32 kHz crystal) 5.10 0.94 7.60 7.90 8.70 127 20 Master 5.10 0.94 6.99 7.20 7.90 n.a. 20 0.13 0.13 0.13 0.13 0.14 5 0 mA mA mA mA mA A A IO Unit 3/25 STLC2411 4 BLOCK DIAGRAM AND ELECTRICAL SCHEMA Figure 2. Block Diagram and Electrical Schematic JTAG VDD 100nF 5 INTERRUPT CONTROLLER PCM 4 2 PCM EXT._INT1/2 VDDIO 100nF USB 2 USB I2C VDDIO 100nF ARM7 TDMI 2 I2C APB BRIDGE SPI 4 SPI RF BUS 13 RADIO I/F BLUETOOTH(R) CORE D M A TIMER GPIO 16 GPIO(O..15) RAM START DETECT UART 8 UART2 (*) 22pF LPOCLKP Y2 32kHz SYSTEM CONTROL LPOCLKN VDD VDDPLL 4 XIN BOOT WAIT RDN/WRN 3 CSN(0..2) EMI 20 16 D02TL550A LPO BOOT ROM UART FIFO UART 2 UART1 22pF 2 NRESET SYS_CLK_REQ VDD 100nF 100nF ADDR(0..19) DATA(0..15) (*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal 4/25 STLC2411 5 PINOUT Figure 3. Pin out (Bottom view) 5 6 7 8 9 10 11 12 13 14 gpio9 gpio11 gpio14 vddio_ brxd bmosi bdclk bpaen brxen ant_sw radio n.c. gpio10 gpio13 n.c. brclk bnden btxd vdd btxen vddio 4 tdi tdo tms 3 ntrst tck 2 test 1 xin A sys_ nreset clk_req B gpio8 vddpll gpio12 gpio15 vssio bmiso bsen vsspll gpio6 gpio7 gpio3 gpio4 gpio5 gpio0 gpio1 gpio2 boot data 14 data 13 data 10 vdd lpo_ lpo_ clk_p clk_n data 15 data 12 data 9 vss wait data 11 vss vdd vdd vss vss bpktctl vssio uart1_ uart1_ i2c_ rxd txd dat C i2c_clk int1 int2 D pcm_ vddio vssio sync E pcm_ clk pcm_a pcm_b F uart2_ usb_ usb_ rxd dp dn G uart2_ uart2_ uart2_ i2 i1 txd H uart2_ uart2_ uart2_ io1 o2 o1 J vss vdd uart2_ io2 K spi_frm vssio vddio csn1 csn2 spi_ txd wrn spi_ clk spi_ rxd rdn P D02TL551 L M N data8 data7 data6 data0 addr17 vss addr13 addr10 addr5 addr2 data5 data4 data2 addr19 addr16 vdd addr12 addr9 addr6 addr3 data3 n.c. data1 addr18 addr15 addr14 addr11 addr8 addr7 addr4 addr1 addr0 csn0 5.1 Pin Description and Assignment Table 9 shows the pin list of the STLC2411. There are 107 digital functional pins and 22 supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This cannot replace an external pull-up/down. The pads are grouped according to three different power supply values, as shown in column "VDD": - V1 for 3.3 V typical 1.65 - 3.6 V range - V1_radio for 3.3 V typical 2.7 - 3.6 V range (for STLC2150 BT radio) - V2 for 1.8 V typical 1.55 - 1.95 V range Note: V1 and V1_radio can be connected together to the same 3.3 V typical supply for STLC2150 BT radio. Finally the column "DIR" describes the pin directions: - I for Inputs - O for Outputs - I/O for Input/Outputs - O/t for tri-state outputs 5/25 STLC2411 Table 9. STLC2411 Pin List Name Pin # Description DIR PU/PD VDD PAD Interface to external memory (supports up to 2 Mbyte Flash and byte access for up to1 Mbyte RAM.) int1 int2 boot wait rdn wrn csn0 csn1 csn2 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 addr19 data0 data1 data2 data3 data4 data5 D2 D1 G14 H12 P1 N2 P2 M3 N3 P3 P4 M5 N5 P5 M6 N6 P6 P7 N7 M7 P8 N8 M8 P9 P10 N10 M10 P11 N11 M11 P12 N12 P14 N13 N14 External Interrupt used also as external wakeup Second external interrupt Select external boot from EMI or internal from ROM EMI external wait signal (left open) External read External write External chip select bank 0 External chip select bank 1 External chip select bank 2 External address bit 0 External address bit 1 External address bit 2 External address bit 3 External address bit 4 External address bit 5 External address bit 6 External address bit 7 External address bit 8 External address bit 9 External address bit 10 External address bit 11 External address bit 12 External address bit 13 External address bit 14 External address bit 15 External address bit 16 External address bit 17 External address bit 18 External address bit 19 External data bit 0 External data bit 1 External data bit 2 External data bit 3 External data bit 4 External data bit 5 I I I I O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O PD PD PD PD PD PD V2 CMOS 1.8V 4mA slew rate control V2 CMOS 1.8V 4mA slew rate control (1) (1) (1) V1 CMOS, 3.3V TTL compatible schmitt trigger CMOS 1.8V V2 PD 6/25 STLC2411 Table 9. STLC2411 Pin List (continued) Name data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 Pin # M12 M13 M14 K13 K14 J12 J13 J14 H14 H13 External data bit 6 External data bit 7 External data bit 8 External data bit 9 External data bit 10 External data bit 11 External data bit 12 External data bit 13 External data bit 14 External data bit 15 Description DIR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PU/PD PD PD PD PD PD V2 PD PD PD PD PD CMOS 1.8V 4mA slew rate control VDD PAD SPI interface spi_frm spi_clk L3 M1 Synchronous Serial Interface frame sync Synchronous Serial Interface clock I/O I/O V1 CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control schmitt trigger CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible schmitt trigger spi_txd M2 Synchronous Serial Interface transmit data O/t V1 spi_rxd N1 Synchronous Serial Interface receive data I (1) V1 UART interface uart1_txd C2 Uart1 transmit data O/t V1 uart1_rxd C3 Uart1 receive data I (2) CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control CMOS, 3.3V TTL compatible, 2mA slew rate control V1 uart2_o1 J1 Uart2 modem output O V1 uart2_o2 J2 Uart2 modem output O/t V1 uart2_i1 uart2_i2 uart2_io1 uart2_io2 H2 H3 J3 K1 Uart2 modem input Uart2 modem input Uart2 modem input/output Uart2 modem input/output I I I/O I/O (2) (2) (2) (2) V1 V1 V1 V1 uart2_txd H1 Uart2 transmit data O/t V1 7/25 STLC2411 Table 9. STLC2411 Pin List (continued) Name uart2_rxd Pin # G3 Description Uart2 receive data DIR I PU/PD (2) VDD V1 PAD CMOS, 3.3V TTL compatible I2C interface i2c_dat i2c_clk C1 D3 I2C data pin I2C clock pin I/O I/O (3) (3) V1 V1 CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control USB interface usb_dn usb_dp G1 G2 USB - pin (Needs a series resistor of 27 5%) USB + pin (Needs a series resistor of 27 5%) I/O I/O (1) (1) V1 V1 GPIO interface gpio0 gpio1 gpio2 gpio3 F14 F13 F12 E14 Gpio port 0 Gpio port 1 Gpio port 2 Gpio port 3 I/O I/O I/O I/O PU PU PU PU V1 V1 CMOS, 3.3V TTL compatible, 4mA tri-state slew rate control CMOS, 3.3V TTL compatible, 4mA tri-state slew rate control schmitt trigger CMOS, 3.3V TTL compatible, 4mA tri-state slew rate control gpio4 gpio5 gpio6 gpio7 gpio8 gpio9 gpio10 gpio11 gpio12 gpio13 gpio14 gpio15 E13 E12 D13 D12 C14 A14 B13 A13 C12 B12 A12 C11 Gpio port 4 Gpio port 5 Gpio port 6 Gpio port 7 Gpio port 8 Gpio port 9 Gpio port 10 Gpio port 11 Gpio port 12 Gpio port 13 Gpio port 14 Gpio port 15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PU PU PU PU PU PU PU PU PU PU PU PU V1 CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control V1 Clock and test pins xin nreset A1 B2 System clock Reset System clock request I I I/O V1 V1 CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control sys_clk_req B1 lpo_clk_p lpo_clk_n G13 G12 Low power oscillator + / Slow clock input Low power oscillator - I O (1) V2 8/25 STLC2411 Table 9. STLC2411 Pin List (continued) Name test Pin # A2 Test mode Description DIR I PU/PD PD VDD V1 PAD CMOS, 3.3V TTL compatible JTAG interface ntrst tck A3 B3 JTAG pin JTAG pin I I PD (1) V1 CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA slew rate control V1 tms tdi tdo C4 A4 B4 JTAG pin JTAG pin JTAG pin (should be left open) I I O/t V1 PCM interface pcm_a pcm_b pcm_sync pcm_clk F2 F1 E1 F3 PCM data PCM data PCM 8kHz sync PCM clock I/O I/O I/O I/O PD PD PD PD V1 V1 PU PU V1 CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control CMOS, 3.3V TTL compatible, 2mA tri-state slew rate control schmitt trigger Radio interface brclk brxd bmiso bnden bmosi bdclk btxd bsen bpaen brxen btxen bpktctl ant_sw B10 A10 C9 B9 A9 A8 B8 C8 A7 A6 B6 C6 A5 Transmit clock Receive data RF serial interface input data RF serial interface control RF serial interface output data RF serial interface clock Transmit data Synthesizer ON Open PLL Receive ON Transmit ON Packet ON Antenna switch I I I O O O O O O O O O O V1_radio (1) Should be strapped to vssio if not used (2) Should be strapped to vddio if not used (3) Must have a 10 kOhm pull-up. (1) (1) V1_radio CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible V1_radio V1_radio CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible, 8mA slew rate control 9/25 STLC2411 Table 9. Pin List (continued) Name Pin # Power Supply vsspll D14 vddpll C13 vdd B7 vdd K2 vdd L12 vdd L14 vdd M4 vdd N9 vddio_radio A11 vddio B5 vddio E3 vddio L1 vss C7 vss K3 vss K12 vss L13 vss M9 vss N4 vssio C5 vssio C10 vssio E2 vssio L2 Description PLL ground 1.8V supply for PLL 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 3.3V Supply voltage radio interface 3.3V Supply voltage digital IO Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground I/O's ground I/O's ground I/O's ground I/O's ground 10/25 STLC2411 6 FUNCTIONAL DESCRIPTION 6.1 Baseband - WLAN coexistence. See also 7.12. WLAN. 6.1.1 Baseband 1.1 Features The baseband is based on Ericsson Technology Licensing Baseband Core (EBC) and it is compliant with the Bluetooth specification 1.1: - - - - - - - - - - - Point to multipoint (up to 7 Slaves) Asynchronous Connection Less (ACL) link support giving data rates up to 721 kbps Synchronous Connection Oriented (SCO) link with support for 2 voice channels over the air interface. Flexible voice format to host and over the air (CVSD, PCM 13/16 bits, A-law, -law) HW support for packet types: DM1, 3, 5; DH1, 3, 5; HV1, 3; DV Scatternet capabilities (Master in one piconet and Slave in the other one; Slave in two piconets). All scatternet v.1.1 errata supported. Ciphering support up to 128 bits key Paging modes R0, R1, R2 Channel Quality Driven Data Rate Full Bluetooth software stack available Low-level link controller 6.1.2 Baseband 1.2 Features The baseband part is also compliant with the Bluetooth specification 1.2: - Extended SCO (eSCO) links: supports EV3 and EV5 packets. See also 7.6. eSCO. - Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave. See also 7.7. AFH. - Faster Connection: Interlaced scan for Page and Inquiry scan, answer FHS at first reception, RSSI used to limit range. See also 7.8. Faster Connection. - QoS Flush. See also 7.9. QoS. - Synchronization: the local and the master BT clock are available via HCI commands for synchronization of parallel applications on different slaves. - L2CAP Flow & Error control - LMP Improvements - LMP SCO handling - Parameter Ranges update 11/25 STLC2411 7 GENERAL SPECIFICATION 7.1 SYSTEM CLOCK The STLC2411 works with a single clock provided on the XIN pin. The value of this external clock should be any integer value from 12 ... 33 MHz 20ppm (overall). 7.1.1 SLOW CLOCK The slow clock is used by the baseband as reference clock during the low power modes. The slow clock requires an accuracy of 250ppm (overall). Several options are foreseen in order to adjust the STLC2411 behaviour according to the features of the radio used: - If the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and no slow clock is provided by the system, a 32 kHz crystal must be used by the STLC2411 (default mode). - If the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and the system provides a slow clock at 32kHz or 3.2kHz, this signal is simply connected to the STLC2411 (lpo_clk_p). - If the system clock (e.g. 13MHz) is provided at all times, the STLC2411 generates from the reference clock an internal 32kHz clock. This mode is not an optimized mode for power consumption. 7.2 BOOT PROCEDURE The boot code instructions are the first that ARM7TDMI executes after a HW reset. All the internal device's registers are set to their default value. There are 2 types of boot: - External memory boot. When boot pin is set to 1 (connected to VDD), the STLC2411 boots on its external memory - UART download boot from ROM. When boot pin is set to 0 (connected to GND), the STLC2411 boots on its internal ROM (needed to download the new firmware in the external memory). When booting on the internal ROM, the STLC2411 will monitor the UART interface for approximately 1.4 second. If there is no request for code downloading during this period, the ROM jumps to external memory. 7.3 CLOCK DETECTION The STLC2411 has an automatic slow clock frequency detection (32kHz, 3.2kHz or none). 7.4 MASTER RESET When the device's reset is held active (nreset is low), uart1_txd and uart2_txd are set to input state. When the nreset returns high, the device starts to boot. Remark: The device should be held in active reset for minimum 20ms in order to guarantee a complete reset of the device. 7.5 INTERRUPTS/WAKE-UP All GPIOs can be used both as external interrupt source and as wake-up source. In addition, the chip can be woken-up by USB, uart1_rxd, uart2_rxd, int1, int2. 7.6 V1.2 detailed functionality - Extended SCO User Perspective - Extended SCO This function gives improved voice quality since it enables the possibility to retransmit lost or corrupted voice packets in both directions. 12/25 STLC2411 Technical perspective - Extended SCO eSCO incorporates CRC, negotiable data rate, negotiable retransmission window and multi-slot packets. Retransmission of lost or corrupted packets during the retransmission window guarantees on-time delivery. Figure 4. eSCO SCO SCO SCO SCO ACL ACL SCO SCO t eSCO retransmission window 7.7 V1.2 detailed functionality - Adaptive Frequency Hopping User Perspective - Adaptive Frequency Hopping In the Bluetooth spec 1.1 the Bluetooth devices hop in the 2.4 GHz band over 79-channels. Since WLAN 802.11 has become popular, there are specification improvements in the 1.2-SIG spec for Bluetooth where the Bluetooth units can avoid the jammed bands and thereby provide an improved co-existence with WLAN. Technical perspective - Adaptive Frequency Hopping Figure 5. AFH AFH(79) f WLAN used frequency t f AFH(19 t First the Master and/or the Slaves identify the jammed channels. The Master decides on the channel distribution and informs the involved slaves. The Master and the Slaves, at a predefined instant, switch to the new channel distribution scheme. No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses the same hop frequency for transmission as for reception. 13/25 STLC2411 7.8 V1.2 detailed functionality - Faster Connection User Perspective - Faster Connection This feature gives the User about 65% faster connection on average when enabled compared to Bluetooth spec 1.1 connection procedure. Technical perspective - Faster Connection The faster Inquiry functionality is based on a removed/shortened random back off and also a new Interlaced Inquiry scan scheme. The faster Page functionality is based on Interlaced Page Scan. 7.9 V1.2 detailed functionality - Quality of Service User Perspective - Quality of Service Small changes to the BT1.1 spec regarding Quality of Service makes a large difference by allowing all QoS parameters to be communicated over HCI to the link manager that enables efficient BW management. Here after a short list of user perspectives: 1) Flush timeout: enables time-bounded traffic such as video streaming to become more robust when the channel degrades. It sets the maximum delay of an L2CAP frame. It does not enable multiple streams in one piconet, or heavy data transfer at the same time. 2) Simple latency control: allows the host to set the poll interval. Provides enough support for HID devices mixed with other traffic in the piconet. 7.10 Low power modes To save power, two low power modes are supported. Depending of the Bluetooth and of the Host's activity, the STLC2411 autonomously decides to use Sleep Mode or Deep Sleep Mode. Table 10. Low power modes Low power mode Sleep Mode Description The STLC2411: - Accepts HCI commands from the Host. - Supports page- and inquiry scans. - Supports Bluetooth links that are in Sniff, Hold or Park. - Can transfer data over Bluetooth links. - The system clock is still active in part of the design. The STLC2411: - Does not accept HCI commands from the Host. - Keeps track of page- and inquiry scan activities. Switches between sleep and active mode when it is time to scan. - Supports Bluetooth links that are in Sniff, Hold or Park. - Does not transfer data over Bluetooth links. - The system clock is not active in any part of the design. Note: Deep Sleep mode is not compatible with a USB transport layer. Deep Sleep Mode Some examples of the low power modes usage: 7.10.1 SNIFF OR PARK The STLC2411 is in active mode with a Bluetooth connection, once the connection is concluded the SNIFF or the PARK is programmed. Once one of these two states is entered the STLC2411 goes in Sleep Mode. After that, the Host may decide to place the STLC2411 in Deep Sleep Mode by putting the UART LINK in low power mode. The Deep Sleep Mode allows smaller power consumption. When the STLC2411 needs to send or receive a packet (e.g. at TSNIFF or at the beacon instant) it will require the clock and it will go in active mode for the needed transmission/reception. Immediately afterwards it will go back to the Deep 14/25 STLC2411 Sleep Mode. If some HCI transmission is needed, the UART link will be reactivated, using one of the two ways explained in 7.5, and the STLC2411 will move from the Deep Sleep Mode to the Sleep Mode. 7.10.2 INQUIRY/PAGE SCAN When only inquiry scan or page scan is enabled, the STLC2411 will go in Sleep Mode or Deep Sleep Mode outside the receiver activity. The selection between Sleep Mode and Deep Sleep Mode depend on the UART activity like in SNIFF or PARK. 7.10.3 NO CONNECTION If the Host places the UART in low power and there is no activity, then the STLC2411 can be placed in Deep Sleep Mode. 7.10.4 ACTIVE LINK When there is an active link (SCO or ACL), the STLC2411 cannot go in Deep Sleep Mode whatever the UART state is. But the STLC2411 baseband is made such that whenever it is possible, depending on the scheduled activity (number of link, type of link, amount of data exchanged), it goes in Sleep Mode. 7.11 SW initiated low power mode A wide set of wake up mechanisms are supported. 7.12 Bluetooth - WLAN coexistence in collocated scenario The coexistence interface uses 4 GPIO pins, when enabled. Bluetooth and WLAN 802.11 b/g technologies occupy the same 2.4 GHz ISM band. STLC2411 implements a set of mechanisms to avoid interference in a collocated scenario. The STLC2411 supports 5 different algorithms in order to provide efficient and flexible simultaneous functionality between the two technologies in collocated scenarios: - Algorithm 1: PTA (Packet Traffic Arbitration) based coexistence algorithm defined in accordance with the IEEE 802.15.2 recommended practice. - Algorithm 2: the WLAN is the master and it indicates to the STLC2411 when not to operate in case of simultaneous use of the air interface. - Algorithm 3: the STLC2411 is the master and it indicates to the WLAN chip when not to operate in case of simultaneous use of the air interface. - Algorithm 4: Two-wire mechanism - Algorithm 5: Alternating Wireless Medium Access (AWMA), defined in accordance with the WLAN 802.11 b/g technologies. The algorithm is selected via HCI command. The default algorithm is algorithm 1. 7.12.1 Algorithm 1: PTA (Packet Traffic Arbitration) The Algorithm is based on a bus connection between the STLC2411 and the WLAN chip: STLC2411 WLAN By using this coexistence interface it's possible to dynamically allocate bandwidth to the two devices when simultaneous operations are required while the full bandwidth can be allocated to one of them in case the other one does not require activity. The algorithm involves a priority mechanism, which allows preserving the quality of certain types of link. A typical application would be to guarantee optimal quality to the Blue- 15/25 STLC2411 tooth voice communication while an intensive WLAN communication is ongoing. Several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for the priority handling. Those algorithms can be activated via specific HCI commands. The combination of a time division multiplexing techniques to share the bandwidth in case of simultaneous operations and of the priority mechanism avoid the interference due to packet collision and it allows the maximization of the 2.4 GHz ISM bandwidth usage for both devices while preserving the quality of some critical types of link. 7.12.2 Algorithm 2: WLAN master In case the STLC2411 has to cooperate, in a collocated scenario, with a WLAN chip not supporting a PTA based algorithm, it's possible to put in place a simpler mechanism. The interface is reduced to 1 line: RF_NOT_ALLOWED STLC2411 WLAN When the WLAN has to operate, it alerts HIGH the RF_NOT_ALLOWED signal and the STLC2411 will not operate while this signals stays HIGH. This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but cannot provide guaranteed quality over the Bluetooth links. 7.12.3 Algorithm 3: Bluetooth master This algorithm represents the symmetrical case of section 7.12.2. Also in this case the interface is reduced to 1 line: RF_NOT_ALLOWED STLC2411 WLAN When the STLC2411 has to operate it alerts HIGH the RF_NOT_ALLOWED signal and the WLAN will not operate while this signals stays HIGH. This mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth, it provides high quality for all Bluetooth links but cannot provide guaranteed quality over the WLAN links. 7.12.4 Algorithm 4: Two-wire mechanism Based on algorithm 2 and 3, the Host decides, on a case-by-case basis, whether WLAN or Bluetooth is master. 7.12.5 Algorithm 5: Alternating Wireless Medium Access (AWMA) AWMA utilizes a portion of the WLAN beacon interval for Bluetooth operations. From a timing perspective, the medium assignment alternates between usage following WLAN procedures and usage following Bluetooth procedures. The timing synchronization between the WLAN and the STLC2411 is done by the HW signal MEDIUM_FREE. 16/25 STLC2411 Table 11. WLAN HW signal assignment WLAN WLAN 1 WLAN 2 WLAN 3 WLAN 4 Scenario 1: PTA TX_ CONFIRM TX_ REQUEST STATUS OPTIONAL_ SIGNAL Scenario 2: WLAN master BT_RF_NOT_ ALLOWED Not used Not used Not used Scenario 3: BT master Not used WLAN_RF_ NOT_ ALLOWED Not used Not used Scenario 4: 2-wire BT_RF_NOT_ ALLOWED WLAN_RF_ NOT_ ALLOWED Not used Not used Scenario 5: AWMA MEDIUM_FREE Not used Not used Not used 8 INTERFACES 8.1 UART Interface The chip contains two enhanced (128 byte transmit FIFO and 128 byte receive FIFO, sleep mode, 127 Rx and 128 Tx interrupt thresholds) UARTs named UART1 and UART2 compatible with the standard M16550 UART. For UART1, only Rx and Tx signals are available (used for debug purposes). UART2 features: - standard HCI UART transport layer: - all HCI commands as described in the BluetoothTM specification 1.1 - ST specific HCI command (check STLC2411 Software Interface document for more information) - RXD, TXD, CTS, RTS on permanent external pins - 128-byte FIFOs, for transmit and for receive - Default configuration: 57.600 kbps - Specific HCI command to change to the following baud rates: Table 12. List of supported baud rates Baud rate - 921.6k 460.8 k 230.4 k 153.6 k 115.2 k 76.8 k 57.600 kbps (default) 38.4 k 28.8 k 19.2 k 14.4 k 9600 7200 4800 2400 1800 1200 900 600 300 8.2 Synchronous Serial Interface The Synchronous Serial Interface (SSI) (or the Synchronous Peripheral Interface (SPI)) is a flexible module supporting full-duplex and half-duplex synchronous communications with external devices in Master and Slave mode. It enables a microcontroller unit to communicate with peripheral devices or allows interprocessor communications in a multiple-master environment. This Interface is compatible with the Motorola SPI standard, with the Texas Instruments Synchronous Serial frame format and with National Semiconductor Microwire standard. Special extensions are implemented to support the Agilent SPI interface for optical mouse applications and the 32 bit data SPI for stereo codec applications. 8.2.1 Feature description: Agilent mode One application is a combination of a Bluetooth device with an AGILENT optical mouse sensor to build a Bluetooth Mouse. The AGILENT chip has an SPI interface with one bi-directional data port. When spi_io from ADNS_2030 is driving, spi_rxd should be active, while spi_txd is set as a tri-state high 17/25 STLC2411 impedance input. For a read operation, the Bluetooth spi_txd is put in high impedance state after the reception of the address. Note that this feature works independently of the SPI mode, supporting other combinations. In this case, the devices are connected as described in the figure below. Figure 6. STLC2411 spi_clk spi_frm spi_txd spi_rxd Agilent ADNS-2030 spi_clk spi_io 8.2.2 Feature description: 32 bit SPI One application is a Bluetooth stereo headset. In this application, the audio samples are received from the emitter through the air using the Bluetooth baseband with ACL packets. The samples are decoded by the embedded ARM CPU (the samples were encoded, for compression, in SBC or MP3 format) and then sent to a stereo codec though the SPI interface. The application is described in the figure below. Figure 7. Bluetooth reception STLC2411 SPI slave mode 32 bits spi_txd spi_r xd spi_frm spi_clk 32 spi_clk 16 spi_clk STw5094A CODEC SPI master mode 32 bits stereo headset To support this application, the data size is 32 bits. The 32 bits support is implemented for both transmit and receive. 8.3 I2C Interface Used to access I2C peripherals. The interface is a fast master I2C; it has full control of the interface at all times. I2C slave functionality is not supported. 18/25 STLC2411 8.4 USB Interface The USB interface is compliant with the USB 2.0 full speed specification. Max throughput on the USB interface is 12 Mbit/s. Figure 8 gives an overview of the main components needed for supporting the USB interface, as specified in the BluetoothTM Core Specification. For clarity, the serial interface (including the UART Transport Layer) is also shown. Figure 8. USB Interface HCI USB TRANSPORT LAYER UART TRANSPORT LAYER USB DEVICE REGISTERS FIFOs USB DRIVER SERIAL DRIVER UART DEVICE REGISTERS FIFOs IRQ RTOS STLC2411 HW The USB device registers and FIFOs are memory mapped. The USB Driver will use these registers to access the USB interface. The equivalent exists for the HCI communication over UART. For transmission to the host, the USB & Serial Drivers interface with the HW via a set of registers and FIFOs, while in the other direction, the hardware may trigger the Drivers through a set of interrupts (identified by the RTOS, and directed to the appropriate Driver routines). 8.5 JTAG Interface The JTAG interface is compliant with the JTAG IEEE Std 1149.1. Its allows both the boundary scan of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 development tools. 8.6 RF Interface The STLC2411 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirectional serial interface for control). 8.7 PCM voice interface The voice interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or STw5094) including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), Law (8bit) or A-Law (8bit). By default the codec interface is configured as master. The encoding on the air D04TL623 IRQ 19/25 STLC2411 interface is programmable to be CVSD, A-Law or -Law. The PCM block is able to manage the PCM bus with up to 3 timeslots. PCM clock and data are in master mode available at 2 MHz or at 2.048 MHz to allow interfacing of standard codecs. The four signals of the PCM interface are: - PCM_CLK : PCM clock - PCM_SYNC : PCM 8kHz sync - PCM_A : PCM data - PCM_B : PCM data Directions of PCM_A and PCM_B are software configurable. Three additional PCM_SYNC signals can be provided via the GPIOs. See section 12 for more details. Figure 9. PCM (A-law, -law) standard mode 0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCM_SYNC PCM_A B B PCM_B B 125s B D02TL558 Figure 10. Linear mode 0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCM_SYNC PCM_A PCM_B 125s D02TL559 Table 13. PCM interface timing. Symbol PCM Interface Fpcm_clk Fpcm_sync tWCH tWCL tWSH tSSC tSDC tHCD tDCD Frequency of PCM_CLK (master) Frequency of PCM_SYNC High period of PCM_CLK Low period of PCM_CLK High period of PCM_SYNC Setup time, PCM_SYNC high to PCM_CLK low Setup time, PCM_A/B input valid to PCM_CLK low Hold time, PCM_CLK low to PCM_A/B input invalid Delay time, PCM_CLK high to PCM_A/B output valid 200 200 200 100 100 100 150 2048 8 kHz kHz ns ns ns ns ns ns ns Description Min Typ Max Unit 20/25 STLC2411 Figure 11. PCM interface timing tWCL PCM_CLK tWCH tSSC PCM_SYNC tWSH tSDC tHCD MSB MSB-1 MSB-2 MSB-3 MSB-4 PCM_A/B in tDCD PCM_B/A out MSB MSB-1 MSB-2 MSB-3 MSB-4 D02TL557 9 HCI UART TRANSPORT LAYER The UART Transport Layer is specified by the BluetoothTM SIG, and allows HCI level communication between a host controller (STLC2411) and a host (e.g. PC), via a serial line. The objective of this HCI UART Transport Layer is to make it possible to use the BluetoothTM HCI over a serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the UART communication is free from line errors. 9.1 UART Settings The HCI UART Transport Layer uses the following settings for RS232: - Baud rate: Configurable (Default baud rate: 57.600 kbps) - Number of data bits: 8 - Parity bit: no parity - Stop bit: 1 stop bit - Flow control: RTS/CTS - Flow-off response time: 3 ms Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for flow control of HCI, since HCI has its own flow control mechanisms for HCI commands, HCI events and HCI data. If CTS is 1, then the Host/Host Controller is allowed to send. If CTS is 0, then the Host/Host Controller is not allowed to send. The flow-off response time defines the maximum time from setting RTS low until the byte flow actually stops. The signals should be connected in a null-modem fashion; i.e. the local TXD should be connected to the remote RXD and the local RTS should be connected to the remote CTS and vice versa. Figure 12. UART Transport Layer BLUETHOOTH HOST BLUETHOOTH HCI BLUETHOOTH HOST CONTROLLER HCI UART TRANSPORT LAYER D02TL556 21/25 STLC2411 10 HCI USB TRANSPORT LAYER The USB Transport Layer has been specified by the BluetoothTM SIG, and allows HCI level communication between a host controller (STLC2411) and a host (e.g. PC), via a USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmission over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Layer does not interprete the contents (payload) of the HCI messages; it only examines the header. 11 CLASS1 POWER SUPPORT The chip can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this purpose in order to avoid digital/analogue noise loops in the radio. A software controlled register enables the alternate functions of GPIO[15:6] to generate the signals for driving an external PA in a BluetoothTM class1 power application. Every bit enables a dedicated signal on a GPIO pin, as described in Table 14. 12 GPIOS Table 14. GPIOs alternate functionalities Involved GPIO gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 gpio9 gpio10] gpio11 gpio12 gpio13 gpio14 gpio15 Description of alternate dedicated functionality No dedicated function WLAN 1 WLAN 2 WLAN 3 WLAN 4 (Used for USB reset pull.) Power Class 1 brxen Power Class 1 not_brxen Power Class 1 PA0 or PCM sync 1 Power Class 1 PA1 or PCM sync 2 Power Class 1 PA2 or PCM sync 3 Power Class 1 PA3 Power Class 1 PA4 Power Class 1 PA5 Power Class 1 PA6 Power Class 1 PA7 The signal brxen is the same as the brxen radio output pin. The signal not_brxen is the inverted signal, in order to save components on the application board. PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the baseband core. The Power Level programmed for a certain BluetoothTM connection is managed by the firmware, as specified in the BluetoothTM SIG spec. The WLAN signals, as described in section 7.12, can be enabled on GPIO pins. The extra PCM sync signals, as described in section 8.7, can be flexibly configured on GPIO pins to connect multiple codecs. 22/25 STLC2411 Figure 13. TFBGA132 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 b D D1 E E1 e f ddd 0.450 0.600 7.850 0.250 7.850 1.010 0.150 0.820 0.300 8.000 6.500 8.000 6.500 0.500 0.750 0.550 0.900 0.080 0.018 0.024 8.150 0.310 0.350 8.150 0.010 0.310 TYP. MAX. 1.200 MIN. 0.040 0.006 0.032 0.012 0.315 0.256 0.315 0.256 0.020 0.029 0.022 0.035 0.003 0.321 0.014 0.321 TYP. MAX. 0.047 inch OUTLINE AND MECHANICAL DATA Body: 8 x 8 x 1.20mm TFBGA132 Fine Pitch Ball Grid Array 7146828 A 23/25 STLC2411 Table 15. Revision History Date June 2004 Revision 1 First Issue Description of Changes 24/25 STLC2411 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. The BLUETOOTHTM word mark and logos are owned by the Bluetooth SIG, Inc. and any use of such marks by STMicroelectronics is under license. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 25/25 |
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